There are not drivers for TEMAC for Zynq. And I can not build Linux for ARCH=arm with LL TEMAC support. There are a lot of errors: flush_dcache_range() and invalidate_dcache_range() are not defined for ARM architecture. The current driver available in the Xilinx Linux distribution is in sync with the open source driver except commits mentioned in 2018.1 changelog. Change Log 2018.2. The problem resides in how these eusb-jtag cable present themselves to the usb host. If you look with a magnifier you see they present twice. The first time as generic usb device looking for firmware, then a specific binary file is sent (through usb-bulk), the cable uploads it, resets, reboots, and presents itself again the usb host as jtag cable. The official Linux kernel from Xilinx. Contribute to Xilinx/linux-xlnx development by creating an account on GitHub.
Active2 years, 11 months ago
Xilinx Cable Driver Windows 10![]()
we are working on a Xilinx Zynq FPGA custom DMA device to process lots of data fast. We were able to make it all work on bare-metal, but have trouble in Linux.We work on ARM linux kernel 3.9. We do not know how to instantiate and use the kernel driver for our device:https://github.com/Xilinx/linux-xlnx/blob/master/drivers/dma/xilinx/xilinx_axidma.cDoes any of you have suggestions or some example code they can share?
Right now we plan to use some of the code here:http://www.mjmwired.net/kernel/Documentation/DMA-API-HOWTO.txt
But we are not sure how to instantiate the struct device.
Ciro Santilli 新疆改造中心996ICU六四事件
168k3636 gold badges644644 silver badges518518 bronze badges
EugeEuge
1 Answer
I think in the xilinx_axidma.c codes, the xdev->dev and chan->dev has already been initialized to &(op->dev). You can pass the xdev->dev or chan->dev as the first parameter to DMA APIs. There is no need to create a DMA buffer pool yourself in the xilinx_axidma.c. In a word, the initialization has been done correctly. You can go ahead to using DMA APIs. Maybe you will create a Tx/Rx buffer ring instead of one buffer. Since the FPGA chip DMA controller uses the physical address, while the kernel module uses the virtual address. So you have to create some kind of structures to maintain both the vaddrs and paddrs for all buffers in the buffer rings, such as BD/buffer approach.
(1) How to allocate one DMA buffer:
The return value is the virtual address of the allocated DMA buffer, and paddr stores the physical address of it. The FPGA chip DMA controller uses the paddr, while the kernel module uses the vaddr.
(2) After received the data from FPGA, call following function to invalidate the D-Cache:
The paddr is the physical address of the DMA buffer.
(3) Before sending one buffer to FPGA, call following function to flush the D-cache:
Xilinx Ise Linux
The paddr is the physical address of the DMA buffer, the vaddr is the virtual address of the DMA buffer.
Linux Device Driver![]()
(4) Get a receive buffer's physical address:
Xilinx Linux Driver
(5) How to free one DMA buffer:
The vaddr is the virtual address of the DMA buffer, whereas the paddr is the physical address.
tian_yufengtian_yufeng
Xilinx Sdk Linux
Got a question that you can’t ask on public Stack Overflow? Learn more about sharing private information with Stack Overflow for Teams.
Nvidia Linux DriverNot the answer you're looking for? Browse other questions tagged linuxkerneldriverfpga or ask your own question.Comments are closed.
|
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |